The basic design constists of a crack engine that has 1 up-stream port and 2 down-stream ports - the upstream port is supposed to be able to be connected to either a parallel port on a PC or the down stream port from another engine - this allows you to create an array of engines structured as a tree attached to a parallel port on a PC, since each engine only needs to be serviced every hour or so (assuming 2^32 blocks are being cracked) polling each entry in a tree is a reasonable approach to array maintenance (and since you can predict when something will complete you can only poll when needed).
The test-bench shows how to put 3 together and write their internal registers, it's set up to test with the RC5 practice keys
Caveat emptor! - while I've tested this in Verilog I haven't built a physical one (not enough time sadly) - look carefully at the code - I've commented out the magic numbers for the real contest and replaced them with the practice keys for testing (search for "practice") make sure you change this back (and understand what you are doing) otherwise you are going to waste an awfull lot of time.
Remember that a 'pass' in this implementation doesn't mean an exact key match, it just means you may be close (the D-net code gets some false positives [I think someone told me 64 over the entire key space] which are resolved by testing back in their lab) it would be usefull to us hardware guys if they'd release the block number of one of those false blocks [if they have any] so we can verify any implementations.
You're free to snarf it and do what you want with it - I just ask for some credit if you make it big, and encourage you to write it up and share your design with others.