Dunedin Makerspace - Tiny-Tapeout Course

We promised a Dunedin Makerspace short course on VLSI design this year, Tiny- Tapeout 3 has just been announced, and it will be the same as the previous one.

This course will be free and open to anyone (but tiny-tapeout itself costs US$25, you can do everything but actually make a chip for free). You will need to bring a laptop and load software onto it before each class.

The course will be 3 weeks, located at Makerspace, 11 Allen St, NEV, 2 hours per night starting at 7pm, there is a general assumption that you have some programming experience, we will be wearing masks during the course:

March 9th: Verilog (a chip design language)

A short talk and then we'll write some verilog

Here's the contents of the talk

Please install the following two pieces of free software on your laptop:

Icarus Verilog - https://steveicarus.github.io/iverilog/ (binary downloads are available, most Linux systems have them easily available through apt/yum/etc)

Gtkwave - https://gtkwave.sourceforge.net/

Homework will be to design and test a simple digital circuit in Verilog to flash some LEDs - the board we're working with has 4 input push buttons and 4 outpout LEDs.

March 16th: FPGAs

we're going to take your design and load it on to an FPGA and try it out, we will have a couple of boards available to share. Mine is available for someone to take home for a week (and someone else the next week).

We'll have a short talk talking about place and route and FPGAs, but mostly we're going to play with stuff.

For today's class I'm going to use a variant of last week's counter example which has a larger counter (because we have a faster clock) and connects some of the the upper 4 bits to 4 external LEDs, we use an extern push button to choose which 4 bits, press the button and it counts faster.

Here's the counter, sel chooses which outputs we use, your homework design will be whatever you want, but at the top level it needs a clock a reset and some inputs/outputs:

module count(
    input clk,
    input reset,
    input sel,
    output [3:0]out
    );
    
    reg [24:0]r_count, c_count;
    
    assign out = !sel?r_count[24:21]:r_count[22:19];
    
    always @(posedge clk)
        r_count <= c_count;
        
    always @(*) begin
        c_count = r_count;
        if (reset) begin
            c_count = 0;
        end else begin
            c_count = r_count+1;
        end
    end
endmodule

We also need add a top level module that hooks up the clock and the external pins, you should make one of these for your homework design, we'll make the clock wizard later:

module top(
    input clk_in_1,
    input sel,
    output out_3,
    output out_2,
    output out_1,
    output out_0
    );

    wire clk;

    clk_wiz_0 c(.clk_in1(clk_in_1), .reset(1'b0), .clkout1(clk));
    count cl(.clk(clk), .reset(1'b0), .sel(sel), .out({out_3, out_2, out_1, out_0}));

endmodule

If possible before the class please install the (free) Xilinix Vivado design software using the following instructions (warning it's going to take ~60Gb and take a while, you can throw it away when you are done)

If you can't fit it on we can share it a little.

Homework will be to refine your design into something we can submit to tiny- tapeout - tiny tapeout designs have a max of 8 input wires, 2 of which must be clk and reset, and 8 output wires

Here's the contents of the talk

March 23rd: Tiny Tapeout

Tiny tapeout is a shared chip run on one of the multi-project shuttles, you can find out more here: https://tinytapeout.com/ and there's a talk here https://www.youtube.com/watch?v=fblSVCPvCiY

It costs US$25 for just a design and US$100 if you want a design, a chip and a PCB - I'll be ordering one of these so if you just order a design you can test it on my PCB when I get it back - or you can spend the extra and get a board of your own.

(in comparison, when I used to do VLSI design for a living a tapeout cost ~$500K, cad design tools cost about as much)

Chips take a long time to build, we likely wont get a PCB back until the end of the year.

To prepare for this class you should obtain a github account, they are free.

Also TinyTapeout 3 designs have 8 input and 8 output wires, 2 of which are hardwired to clock and reset, convert the design you want to tape out so that it looks like this:

module my_design (input [7:0] io_in, output [7:0] io_out);

    wire clk = io_in[0];
    wire reset = io_in[1];

    ....

Here's the contents of the talk

This is not just for Makerspace members, so please pass this around to others who may be interested. If you missed it you're welcome to come in to Makerspace and we'll walk you through it. There will likely be a new Tiny Tapeout in about 3 months.

Contact Paul Campbell (021)512614 for any questions